SIA918EDJ www.vishay.com vishay siliconix s16-1004-rev. a, 30-may-16 1 document number: 79034 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 dual n-channel 30 v (d-s) mosfet marking code: cl ordering information: ? SIA918EDJ-t1-ge3 (lead (pb)-free and halogen free) features ? trenchfet ? power mosfet ? thermally enhanced powerpak ? sc-70 package ? - small footprint area ? - low on-resistance ? typical esd protection: 1000 v (hbm) ? 100 % r g tested ? material categorization: fo r definitions of compliance please see www.vishay.com/doc?99912 applications ? portable devices such as smart phones, tablet pcs and mobile computing ? - load switch ? - dc/dc converter ? - power management notes a. package limited. b. surface mounted on 1" x 1" fr4 board. c. t = 5 s. d. see solder profile ( www.vishay.com/doc?73257 ). the powerpak sc-70 is a leadless package. the end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. a solder fillet at the exposed copper tip cannot b e guaranteed and is not required to ensure adequa te bottom side sold er interconnection. e. rework conditions: manual soldering with a solderin g iron is not recommended for leadless components. f. maximum under steady stat e condition is 110 c/w. product summary v ds (v) r ds(on) ( ? ) max. i d (a) q g (typ.) 30 0.058 at v gs = 4.5 v 4.5 a 3.6 nc 0.065 at v gs = 2.5 v 4.5 a 0.077 at v gs = 1.8 v 4.5 a powerpak ? s c-70-6l dual top view 2.05 mm 2.05 mm 1 205 2 05 mm 2.05 mm 1 1 bottom view 3 d 2 2 g 1 1 s 1 d 1 d 2 s 2 4 g 2 5 d 1 6 n-channel mosfet n-channel mosfet s 2 d 2 g 2 s 1 d 1 g 1 absolute maximum ratings (t a = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds 30 v gate-source voltage v gs 8 continuous drain current (t j = 150 c) t c = 25 c i d 4.5 a a t c = 70 c 4.5 a t a = 25 c 4.4 b, c t a = 70 c 3.5 b, c pulsed drain current (t = 100 s) i dm 15 continuous source-drain diode current t c = 25 c i s 4.5 a t a = 25 c 1.6 b, c maximum power dissipation t c = 25 c p d 7.8 w t c = 70 c 5 t a = 25 c 1.9 b, c t a = 70 c 1.2 b, c operating junction and storage temperature range t j , t stg -55 to +150 c soldering recommendations (peak temperature) d,e 260 thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient b, f t ? 5 s r thja 52 65 c/w maximum junction-to-case (drain) steady state r thjc 12.5 16
SIA918EDJ www.vishay.com vishay siliconix s16-1004-rev. a, 30-may-16 2 document number: 79034 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes a. pulse test; pulse width ? 300 s, duty cycle ? 2 %. b. guaranteed by design, not su bject to production testing. stresses beyond those listed under absolute maximum ratings ma y cause permanent damage to th e device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those in dicated in the operational sectio ns of the specifications is not implied. exposure to absolute maximum rating conditions for extended pe riods may affect device reliability. specifications (t j = 25 c, unless otherwise noted) parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a 30 - - v v ds temperature coefficient ? v ds /t j i d = 250 a -28 - mv/c v gs(th) temperature coefficient ? v gs(th) /t j --2.4 - gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 0.4 - 0.9 v gate-source leakage i gss v ds = 0 v, v gs = 4.5 v - - 0.5 a v ds = 0 v, v gs = 8 v - - 5 zero gate voltage drain current i dss v ds = 30 v, v gs = 0 v - - 1 v ds = 30 v, v gs = 0 v, t j = 55 c - - 10 on-state drain current a i d(on) v ds ? 5 v, v gs = 4.5 v 10 - - a drain-source on-state resistance a r ds(on) v gs = 4.5 v, i d = 3 a - 0.046 0.058 ? v gs = 2.5 v, i d = 3 a - 0.050 0.065 v gs = 1.8 v, i d = 1 a - 0.055 0.077 forward transconductance a g fs v ds = 15 v, i d = 3 a - 14 - s dynamic b total gate charge q g v ds = 15 v, v gs = 8 v, i d = 10 a - 6.2 9.5 nc v ds = 15 v, v gs = 4.5 v, i d = 10 a -3.65.5 gate-source charge q gs -0.45 - gate-drain charge q gd -0.53 - gate resistance r g f = 1 mhz 0.9 4.3 8.6 ? turn-on delay time t d(on) v dd = 15 v, r l = 5 ? i d ? 3 a, v gen = 4.5 v, r g = 1 ? -510 ns rise time t r -3060 turn-off delay time t d(off) -3060 fall time t f -4180 turn-on delay time t d(on) v dd = 15 v, r l = 5 ? i d ? 3 a, v gen = 8 v, r g = 1 ? -2 5 rise time t r -2350 turn-off delay time t d(off) -1120 fall time t f -2650 drain-source body diode characteristics continuous source-drain diode current i s t c = 25 c - - 4.5 a pulse diode forward current i sm --15 body diode voltage v sd i s = 3 a, v gs = 0 v - 0.84 1.2 v body diode reverse recovery time t rr i f = 3 a, di/dt = 100 a/s, t j = 25 c -1120 ns body diode reverse recovery charge q rr -4.410 nc reverse recovery fall time t a -8 - ns reverse recovery rise time t b -3 -
SIA918EDJ www.vishay.com vishay siliconix s16-1004-rev. a, 30-may-16 3 document number: 79034 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) gate current vs. gate-source voltage output characteristics on-resistance vs. drain current and gate voltage gate current vs. gate-source voltage transfer characteristics capacitance 10 100 1000 10000 0 3.0 6.0 9.0 12.0 15.0 0 2 4 6 8 10 12 14 16 axis title 1st line 2nd line 2nd line i gss - gate current (ma) v gs - gate-to-source voltage (v) 2nd line t j = 25 c 10 100 1000 10000 0 3 6 9 12 15 0 0.5 1 1.5 2 2.5 3 axis title 1st line 2nd line 2nd line i d - drain current (a) v ds - drain-to-source voltage (v) 2nd line v gs = 5 v thru 2 v v gs = 1 v v gs = 1.5 v 10 100 1000 10000 0 0.03 0.06 0.09 0.12 03691215 axis title 1st line 2nd line 2nd line r ds(on) - on-resistance () i d - drain current (a) 2nd line v gs = 1.8 v v gs = 4.5 v v gs = 2.5 v 10 -2 10 -3 10 -4 10 -5 10 -6 10 -7 10 -8 10 -9 10 -10 10 100 1000 10000 03691215 axis title 1st line 2nd line 2nd line i gss - gate current (a) v gs - gate-to-source voltage (v) 2nd line t j = 150 c t j = 25 c 10 100 1000 10000 0 3 6 9 12 15 0 0.5 1 1.5 2 axis title 1st line 2nd line 2nd line i d - drain current (a) v gs - gate-to-source voltage (v) 2nd line t c = 25 c t c =-55 c t c = 125 c 10 100 1000 10000 0 100 200 300 400 500 0 5 10 15 20 25 30 axis title 1st line 2nd line 2nd line c - capacitance (pf) v ds - drain-to-source voltage (v) 2nd line c rss c oss c iss
SIA918EDJ www.vishay.com vishay siliconix s16-1004-rev. a, 30-may-16 4 document number: 79034 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) gate charge source-drain diode forward voltage threshold voltage on-resistance vs. junction temperature on-resistance vs. gate-to-source voltage single pulse power (junction-to-ambient) 10 100 1000 10000 0 2 4 6 8 0123456 axis title 1st line 2nd line 2nd line v gs - gate-to-source voltage (v) q g - total gate charge (nc) 2nd line v ds = 15 v v ds = 24 v v ds = 7.5 v i d = 10 a 10 100 1000 10000 0.1 1 10 100 0 0.2 0.4 0.6 0.8 1.0 1.2 axis title 1st line 2nd line 2nd line i s - source current (a) v sd - source-to-drain voltage (v) 2nd line t j = 150 c t j = 25 c 10 100 1000 10000 0.2 0.3 0.4 0.5 0.6 0.7 0.8 -50 -25 0 25 50 75 100 125 150 axis title 1st line 2nd line 2nd line v gs(th) (v) t j - temperature (c) 2nd line i d = 250 a 10 100 1000 10000 0.6 0.8 1.0 1.2 1.4 1.6 1.8 -50-25 0 255075100125150 axis title 1st line 2nd line 2nd line r ds(on) - on-resistance (normalized) t j - junction temperature (c) 2nd line i d = 3 a v gs = 4.5 v; 2.5 v v gs = 1.8 v 10 100 1000 10000 0 0.03 0.06 0.09 0.12 012345 axis title 1st line 2nd line 2nd line r ds(on) - on-resistance () v gs - gate-to-source voltage (v) 2nd line t j = 25 c t j = 125 c i d = 7 a 1000 100 10 1 0.001 0.01 0.1 power (w) pulse (s) 20 10 5 15 0
SIA918EDJ www.vishay.com vishay siliconix s16-1004-rev. a, 30-may-16 5 document number: 79034 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) safe operating area, junction-to-ambient current derating a power derating note a. the power dissipation p d is based on t j (max.) = 150 c, using junction-t o-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. it is used to determine the cu rrent rating, when this rating falls below the package limit. 10 100 1000 10000 0.01 0.1 1 10 100 0.1 1 10 100 axis title 1st line 2nd line 2nd line i d - drain current (a) v ds - drain-to-source voltage (v) (1) v gs > minimum v gs at which r ds(on) is specified limited by r ds(on) (1) t a = 25 c single pulse 100 ms 10 ms 1 ms 100 s 1s 10 s dc bvdss limited i dm limited 10 100 1000 10000 0 2 4 6 8 10 0255075100125150 axis title 1st line 2nd line 2nd line i d - drain current (a) t c - case temperature (c) 2nd line package limited 0 2 4 6 8 25 50 75 100 125 150 t c - case temperature (c) power dissipation (w)
SIA918EDJ www.vishay.com vishay siliconix s16-1004-rev. a, 30-may-16 6 document number: 79034 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) normalized thermal transient impedance, junction-to-ambient normalized thermal transient impedance, junction-to-case ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? vishay siliconix maintains worldw ide manufacturing ca pability. products may be manufactured at one of several qualified locatio ns. reliability da ta for silicon technology and package reliability represent a composite of all qu alified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?79034 . 1 0.1 0.01 normalized ef fective t ransient thermal impedance 10 -3 10 -2 0 0 0 1 0 1 1 10 -1 10 -4 100 sq u are w ave p u lse d u ration (s) single p u lse 0.02 0.05 0.1 0.2 d u ty cycle = 0.5 1. d u ty cycle, d = 2. per unit base = r th ja = 110 c/ w 3. t jm - t a = p dm z th ja (t) t 1 t 2 t 1 t 2 notes: 4. s u rface mo u nted p dm 10 -3 10 -2 10 -1 10 -4 1 0.01 sq u are w ave p u lse d u ration (s) normalized ef fective t ransient thermal impedance d u ty cycle = 0.5 0.2 0.1 single p u lse 0.02 0.05
vishay siliconix package information document number: 73001 06-aug-07 www.vishay.com 1 powerpak ? sc70-6l dim single pad dual pad millimeters inches millimeters inches min nom max min nom max min nom max min nom max a 0.675 0.75 0.80 0.027 0.030 0.032 0.675 0.75 0.80 0.027 0.030 0.032 a1 0 - 0.05 0 - 0.002 0 - 0.05 0 - 0.002 b 0.23 0.30 0.38 0.009 0.012 0.015 0.23 0.30 0.38 0.009 0.012 0.015 c 0.15 0.20 0.25 0.006 0.008 0.010 0.15 0.20 0.25 0.006 0.008 0.010 d 1.98 2.05 2.15 0.078 0.081 0.085 1.98 2.05 2.15 0.078 0.081 0.085 d1 0.85 0.95 1.05 0.033 0.037 0.041 0.513 0.613 0.713 0.020 0.024 0.028 d2 0.135 0.235 0.335 0.005 0.009 0.013 e 1.98 2.05 2.15 0.078 0.081 0.085 1.98 2.05 2.15 0.078 0.081 0.085 e1 1.40 1.50 1.60 0.055 0.059 0.063 0.85 0.95 1.05 0.033 0.037 0.041 e2 0.345 0.395 0.445 0.014 0.016 0.018 e3 0.425 0.475 0.525 0.017 0.019 0.021 e 0.65 bsc 0.026 bsc 0.65 bsc 0.026 bsc k 0.275 typ 0.011 typ 0.275 typ 0.011 typ k1 0.400 typ 0.016 typ 0.320 typ 0.013 typ k2 0.240 typ 0.009 typ 0.252 typ 0.010 typ k3 0.225 typ 0.009 typ k4 0.355 typ 0.014 typ l 0.175 0.275 0.375 0.007 0.011 0.015 0.175 0.275 0.375 0.007 0.011 0.015 t 0.05 0.10 0.15 0.002 0.004 0.006 ecn: c-07431 ? rev. c, 06-aug-07 dwg: 5934 e2 back s ide view of s ingle back s ide view of dual note s : 1. all dimen s ion s a re in millimeter s 2. p a ck a ge o u tline excl us ive of mold fl as h a nd met a l bu rr 3 . p a ck a ge o u tline incl us ive of pl a ting pin1 pin6 pin5 pin4 pin2 pin 3 a z detail z z d e k1 k2 c a1 k 3 k2 k2 e b b e pin6 pin5 pin4 pin1 pin 3 pin2 e1 e1 e1 l l k4 k k k d1 d2 d1 d1 k1 e 3
application note 826 vishay siliconix www.vishay.com document number: 70487 1 revision: 18-oct-13 application note recommended pad layout for powerpak ? sc70-6l dual 1 2.500 (0.09 8 ) 0.350 (0.014) 0.275 (0.011) 0.613 (0.024) 0.300 (0.012) 0.325 (0.013) 0.950 (0.037) 0.475 (0.019) 2.500 (0.09 8 ) 0.275 (0.011) 0.160 (0.006) 1.600 (0.063) dimensions in mm (inches) 0.650 (0.026) return to index
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